1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit devices and, more specifically, to an integrated circuit device (e.g., a static random access memory (SRAM) array) and method of forming the device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section.
2. Description of the Related Art
Integrated circuit devices, such as static random access memory (SRAM) arrays or other devices that incorporate both P-type field effect transistors (PFETs) and N-type field effect transistors (NFETs), can be formed on various different types of substrates (e.g., on silicon-on-insulator (SOI) wafers, bulk wafers or hybrid orientation (HOT) wafers). One technique for forming an integrated circuit device on a bulk semiconductor wafer (e.g., a P-wafer) requires implantation of N+ and P+ well regions at the top surface of a bulk wafer prior to epitaxially growing a semiconductor layer. Then, within the epitaxially grown semiconductor layer, PFETs are formed above the N+ well regions and NFETs are formed above the P+ well regions such that the P+ and N+ well regions, respectively, electrically isolate the NFETs and the PFETs from the bulk substrate. Conventionally, shallow trench isolation (STI) regions are used for any required intra-well isolation (i.e., isolation between same conductivity type FETs) and dual depth trench isolation (DDTI) regions, which include deep trench isolation (DTI) regions extending into the substrate below the level of the wells, are used for inter-well isolation (i.e., isolation between different conductivity type FETs). However, having both STI and DDTI regions can be expensive.